mirror of
https://github.com/prometheus/node_exporter.git
synced 2024-11-24 22:06:49 +01:00
337 lines
12 KiB
Go
337 lines
12 KiB
Go
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// +build linux
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package perf
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import (
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"go.uber.org/multierr"
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"golang.org/x/sys/unix"
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)
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const (
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// L1DataReadHit is a constant...
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L1DataReadHit = (unix.PERF_COUNT_HW_CACHE_L1D) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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// L1DataReadMiss is a constant...
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L1DataReadMiss = (unix.PERF_COUNT_HW_CACHE_L1D) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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// L1DataWriteHit is a constant...
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L1DataWriteHit = (unix.PERF_COUNT_HW_CACHE_L1D) | (unix.PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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// L1InstrReadMiss is a constant...
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L1InstrReadMiss = (unix.PERF_COUNT_HW_CACHE_L1I) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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// LLReadHit is a constant...
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LLReadHit = (unix.PERF_COUNT_HW_CACHE_LL) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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// LLReadMiss is a constant...
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LLReadMiss = (unix.PERF_COUNT_HW_CACHE_LL) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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// LLWriteHit is a constant...
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LLWriteHit = (unix.PERF_COUNT_HW_CACHE_LL) | (unix.PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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// LLWriteMiss is a constant...
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LLWriteMiss = (unix.PERF_COUNT_HW_CACHE_LL) | (unix.PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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// DataTLBReadHit is a constant...
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DataTLBReadHit = (unix.PERF_COUNT_HW_CACHE_DTLB) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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// DataTLBReadMiss is a constant...
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DataTLBReadMiss = (unix.PERF_COUNT_HW_CACHE_DTLB) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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// DataTLBWriteHit is a constant...
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DataTLBWriteHit = (unix.PERF_COUNT_HW_CACHE_DTLB) | (unix.PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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// DataTLBWriteMiss is a constant...
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DataTLBWriteMiss = (unix.PERF_COUNT_HW_CACHE_DTLB) | (unix.PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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// InstrTLBReadHit is a constant...
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InstrTLBReadHit = (unix.PERF_COUNT_HW_CACHE_ITLB) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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// InstrTLBReadMiss is a constant...
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InstrTLBReadMiss = (unix.PERF_COUNT_HW_CACHE_ITLB) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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// BPUReadHit is a constant...
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BPUReadHit = (unix.PERF_COUNT_HW_CACHE_BPU) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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// BPUReadMiss is a constant...
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BPUReadMiss = (unix.PERF_COUNT_HW_CACHE_BPU) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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// NodeCacheReadHit is a constant...
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NodeCacheReadHit = (unix.PERF_COUNT_HW_CACHE_NODE) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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// NodeCacheReadMiss is a constant...
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NodeCacheReadMiss = (unix.PERF_COUNT_HW_CACHE_NODE) | (unix.PERF_COUNT_HW_CACHE_OP_READ << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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// NodeCacheWriteHit is a constant...
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NodeCacheWriteHit = (unix.PERF_COUNT_HW_CACHE_NODE) | (unix.PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)
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// NodeCacheWriteMiss is a constant...
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NodeCacheWriteMiss = (unix.PERF_COUNT_HW_CACHE_NODE) | (unix.PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (unix.PERF_COUNT_HW_CACHE_RESULT_MISS << 16)
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)
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type cacheProfiler struct {
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// map of perf counter type to file descriptor
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profilers map[int]Profiler
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}
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// NewCacheProfiler returns a new cache profiler.
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func NewCacheProfiler(pid, cpu int, opts ...int) CacheProfiler {
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profilers := map[int]Profiler{}
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// L1 data
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op := unix.PERF_COUNT_HW_CACHE_OP_READ
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result := unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS
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l1dataReadHit, err := NewL1DataProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[L1DataReadHit] = l1dataReadHit
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_MISS
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l1dataReadMiss, err := NewL1DataProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[L1DataReadMiss] = l1dataReadMiss
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_WRITE
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result = unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS
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l1dataWriteHit, err := NewL1DataProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[L1DataWriteHit] = l1dataWriteHit
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}
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// L1 instruction
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_MISS
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l1InstrReadMiss, err := NewL1InstrProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[L1InstrReadMiss] = l1InstrReadMiss
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}
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// Last Level
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS
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llReadHit, err := NewLLCacheProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[LLReadHit] = llReadHit
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_MISS
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llReadMiss, err := NewLLCacheProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[LLReadMiss] = llReadMiss
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_WRITE
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result = unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS
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llWriteHit, err := NewLLCacheProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[LLWriteHit] = llWriteHit
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_WRITE
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result = unix.PERF_COUNT_HW_CACHE_RESULT_MISS
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llWriteMiss, err := NewLLCacheProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[LLWriteMiss] = llWriteMiss
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}
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// dTLB
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS
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dTLBReadHit, err := NewDataTLBProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[DataTLBReadHit] = dTLBReadHit
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_MISS
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dTLBReadMiss, err := NewDataTLBProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[DataTLBReadMiss] = dTLBReadMiss
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_WRITE
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result = unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS
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dTLBWriteHit, err := NewDataTLBProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[DataTLBWriteHit] = dTLBWriteHit
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_WRITE
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result = unix.PERF_COUNT_HW_CACHE_RESULT_MISS
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dTLBWriteMiss, err := NewDataTLBProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[DataTLBWriteMiss] = dTLBWriteMiss
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}
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// iTLB
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS
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iTLBReadHit, err := NewInstrTLBProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[InstrTLBReadHit] = iTLBReadHit
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_MISS
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iTLBReadMiss, err := NewInstrTLBProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[InstrTLBReadMiss] = iTLBReadMiss
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}
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// BPU
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS
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bpuReadHit, err := NewBPUProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[BPUReadHit] = bpuReadHit
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_MISS
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bpuReadMiss, err := NewBPUProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[BPUReadMiss] = bpuReadMiss
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}
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// Node
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS
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nodeReadHit, err := NewNodeCacheProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[NodeCacheReadHit] = nodeReadHit
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_READ
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result = unix.PERF_COUNT_HW_CACHE_RESULT_MISS
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nodeReadMiss, err := NewNodeCacheProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[NodeCacheReadMiss] = nodeReadMiss
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_WRITE
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result = unix.PERF_COUNT_HW_CACHE_RESULT_ACCESS
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nodeWriteHit, err := NewNodeCacheProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[NodeCacheWriteHit] = nodeWriteHit
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}
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op = unix.PERF_COUNT_HW_CACHE_OP_WRITE
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result = unix.PERF_COUNT_HW_CACHE_RESULT_MISS
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nodeWriteMiss, err := NewNodeCacheProfiler(pid, cpu, op, result, opts...)
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if err == nil {
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profilers[NodeCacheWriteMiss] = nodeWriteMiss
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}
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return &cacheProfiler{
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profilers: profilers,
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}
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}
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// Start is used to start the CacheProfiler, it will return an error if no
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// profilers are configured.
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func (p *cacheProfiler) Start() error {
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if len(p.profilers) == 0 {
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return ErrNoProfiler
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}
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var err error
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for _, profiler := range p.profilers {
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err = multierr.Append(err, profiler.Start())
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}
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return err
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}
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// Reset is used to reset the CacheProfiler.
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func (p *cacheProfiler) Reset() error {
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var err error
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for _, profiler := range p.profilers {
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err = multierr.Append(err, profiler.Reset())
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}
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return err
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}
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// Stop is used to reset the CacheProfiler.
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func (p *cacheProfiler) Stop() error {
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var err error
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for _, profiler := range p.profilers {
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err = multierr.Append(err, profiler.Stop())
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}
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return err
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}
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// Close is used to reset the CacheProfiler.
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func (p *cacheProfiler) Close() error {
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var err error
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for _, profiler := range p.profilers {
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err = multierr.Append(err, profiler.Close())
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}
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return err
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}
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// Profile is used to read the CacheProfiler CacheProfile it returns an
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// error only if all profiles fail.
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func (p *cacheProfiler) Profile() (*CacheProfile, error) {
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var err error
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cacheProfile := &CacheProfile{}
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for profilerType, profiler := range p.profilers {
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profileVal, err2 := profiler.Profile()
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err = multierr.Append(err, err2)
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if err2 == nil {
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if cacheProfile.TimeEnabled == nil {
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cacheProfile.TimeEnabled = &profileVal.TimeEnabled
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}
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if cacheProfile.TimeRunning == nil {
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cacheProfile.TimeRunning = &profileVal.TimeRunning
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}
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switch {
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// L1 data
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case (profilerType ^ L1DataReadHit) == 0:
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cacheProfile.L1DataReadHit = &profileVal.Value
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case (profilerType ^ L1DataReadMiss) == 0:
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cacheProfile.L1DataReadMiss = &profileVal.Value
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case (profilerType ^ L1DataWriteHit) == 0:
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cacheProfile.L1DataWriteHit = &profileVal.Value
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// L1 instruction
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case (profilerType ^ L1InstrReadMiss) == 0:
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cacheProfile.L1InstrReadMiss = &profileVal.Value
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// Last Level
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case (profilerType ^ LLReadHit) == 0:
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cacheProfile.LastLevelReadHit = &profileVal.Value
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case (profilerType ^ LLReadMiss) == 0:
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cacheProfile.LastLevelReadMiss = &profileVal.Value
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case (profilerType ^ LLWriteHit) == 0:
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cacheProfile.LastLevelWriteHit = &profileVal.Value
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case (profilerType ^ LLWriteMiss) == 0:
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cacheProfile.LastLevelWriteMiss = &profileVal.Value
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// dTLB
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case (profilerType ^ DataTLBReadHit) == 0:
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cacheProfile.DataTLBReadHit = &profileVal.Value
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case (profilerType ^ DataTLBReadMiss) == 0:
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cacheProfile.DataTLBReadMiss = &profileVal.Value
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case (profilerType ^ DataTLBWriteHit) == 0:
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cacheProfile.DataTLBWriteHit = &profileVal.Value
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case (profilerType ^ DataTLBWriteMiss) == 0:
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cacheProfile.DataTLBWriteMiss = &profileVal.Value
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// iTLB
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||
|
|
case (profilerType ^ InstrTLBReadHit) == 0:
|
||
|
|
cacheProfile.InstrTLBReadHit = &profileVal.Value
|
||
|
|
case (profilerType ^ InstrTLBReadMiss) == 0:
|
||
|
|
cacheProfile.InstrTLBReadMiss = &profileVal.Value
|
||
|
|
|
||
|
|
// BPU
|
||
|
|
case (profilerType ^ BPUReadHit) == 0:
|
||
|
|
cacheProfile.BPUReadHit = &profileVal.Value
|
||
|
|
case (profilerType ^ BPUReadMiss) == 0:
|
||
|
|
cacheProfile.BPUReadMiss = &profileVal.Value
|
||
|
|
|
||
|
|
// node
|
||
|
|
case (profilerType ^ NodeCacheReadHit) == 0:
|
||
|
|
cacheProfile.NodeReadHit = &profileVal.Value
|
||
|
|
case (profilerType ^ NodeCacheReadMiss) == 0:
|
||
|
|
cacheProfile.NodeReadMiss = &profileVal.Value
|
||
|
|
case (profilerType ^ NodeCacheWriteHit) == 0:
|
||
|
|
cacheProfile.NodeWriteHit = &profileVal.Value
|
||
|
|
case (profilerType ^ NodeCacheWriteMiss) == 0:
|
||
|
|
cacheProfile.NodeWriteMiss = &profileVal.Value
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if len(multierr.Errors(err)) == len(p.profilers) {
|
||
|
|
return nil, err
|
||
|
|
}
|
||
|
|
|
||
|
|
return cacheProfile, nil
|
||
|
|
}
|